The present invention relates to integrated circuits (IC) and, more particularly, to a variable frequency relaxation oscillator.
FIG. 1 is a simplified schematic circuit diagram of a conventional relaxation oscillator 100. The oscillator 100 receives a frequency control signal 100i, which determines an output oscillation frequency, and outputs an oscillation signal 100o, whose frequency depends on the received frequency control signal 100i and which may be used as a clock signal. The oscillator 100 has a set/reset (SR) latch 101 and two oscillator sub-circuits 102. The SR latch 101 has a set (S) input, a reset (R) input, a Q output, and a complementary QB output.
Each oscillator sub-circuit 102 receives (i) the frequency control signal 100i, (ii) a drain supply voltage VDD, (iii) a source supply voltage VSS, and (iv) a reference voltage VREF. The oscillator 100 uses the two substantially identical oscillator sub-circuits 102, rather than just a single oscillator sub-circuit, since the symmetry of the two sub-circuits 102 may make it easier to match the characteristics of the high and low segments of the resultant oscillator output signal 100o. 
Each oscillator sub-circuit 102 outputs a respective output signal 102o, where the output signal 102o(1) of the sub-circuit 102(1) is applied to the R input of the SR latch 101 and the output signal 102o(2) of the sub-circuit 102(2) is applied to the S input of the SR latch 101. The SR latch 101 operates such that if the S input signal 102o(2) is high and the R input signal 102o(1) is low, then the Q output 100o is high and the QB output 101a is low, and if the R input signal 102o(1) is high and the S input signal 102o(2) is low, then the Q output 100o is low and the QB output 101a is high.
Each oscillator sub-circuit 102 comprises a current source 103, a n-channel field-effect transistor (FET) 104 having drain, source, and gate terminals, a variable capacitor 105 having first and second terminals and a control input, and a comparator 106 having positive and negative inputs and an output.
The current source 103 receives the drain supply voltage VDD and outputs a current to a node 107, which is connected to (i) the drain terminal of the FET 104, (ii) the first terminal of the variable capacitor 105, and (iii) the positive input of the comparator 106. The source supply voltage VSS is connected to the source of the FET 104 and the second terminal of the capacitor 105. The negative input of the comparator 106 is connected to the reference voltage VREF. The capacitance of the variable capacitor 105 is controlled by the input signal 100i, which is connected to the control input of the variable capacitor 105. The gate terminal of each FET 104 is connected to a corresponding output of the SR latch 101, where the gate of the FET 104(1) is controlled by the QB output 101a and the gate of the FET 104(2) is controlled by the Q output 100o. 
FIG. 2 is a timing diagram for some of the signals of the oscillator 100 of FIG. 1, namely the frequency control signal 100i, the voltages at the two nodes 107(1) and 107(2), and the output signal 100o. At time t0, the Q output 100o is high and the QB output 101a is low. As a result, FET 104(2), which is controlled by the Q output signal 100o, is ON, and FET 104(1), which is controlled by the QB output signal 101a, is OFF. Accordingly, the voltage V107(2) at the node 107(2) is held at or near to the source supply voltage VSS, which is zero volts, via the turned-on FET 104(2). Since the capacitor 105(2) is not charging, the sub-circuit 102(2) may be considered to be in an idle state at this time. Meanwhile, the voltage V107(1) at the node 107(1) rises steadily as current is provided to the first terminal of the capacitor 105(1) by the current source 103(1).
The reference voltage VREF in FIG. 2 is approximately 0.4 volts. At time t1, when the voltage V107(1) increases above the reference voltage VREF, and the output 102o(1) of the comparator 106(1)—provided to the R input of the SR latch 101—goes from low to high. Note that the output 102o(2) of the comparator 106(2), which is provided to the S input of the SR latch 101, remains low because the voltage V107(2) remains below the reference voltage VREF at time t1. As a result of the switch in the output 102o(1) of the comparator 106(1) at time t1, the Q output 100o goes from high to low and, correspondingly, the QB output 101a goes from low to high. Since the FET 104(1) is turned on when the QB output 101a goes from low to high, the capacitor 105(1) is discharged, and the voltage V107(1) at the node 107(1) drops down substantially to the source supply voltage VSS. Since, as a result, the voltage V107(1) returns to being less than the reference voltage VREF, the output 102o(1) of the comparator 106(1) correspondingly returns to low.
Between time t1 and time t2, the FET 104(2) is off, and the FET 104(1) is on. Consequently, similar to the above-described operation, the voltage V107(2) at the node 107(2) rises steadily while the voltage V107(1) at the node 107(1) is held at or near the source supply voltage VSS. During this time, the sub-circuit 102(1) may be considered to be in an idle state. Then, at time t2, similar to the above-described operation, the voltage V107(2) exceeds the reference voltage VREF and, as a result, the output 102o(2) of the comparator 106(2)—provided to the S input of the SR latch 101—goes from low to high. As a result, the Q output 100o of the SR latch 101 goes from low to high, the QB output 101a goes from high to low, the FET 104(2) is turned on, the capacitor 105(2) is discharged, the FET 104(1) is turned off, and the above-described cycle then repeats.
At time t3, the frequency control signal 100i changes to set a new, higher value for the capacitance of the variable capacitors 105. Because the charging rates of the variable capacitors 105 depends on their respective capacitance, increasing the capacitance value of the variable capacitors 105 lengthens the cycle period and, correspondingly, lowers the cycle frequency of the output signal 100o. Because the capacitance of the variable capacitors 105 is changed mid-operation, a glitch occurs between time t3 and time t4, where the voltage V107(1) briefly spikes over the reference voltage VREF, and the period of the output signal 100o is clipped before normal operation—now at the new, lower frequency—is resumed at time t4.
As used herein, a glitch refers to a half-cycle-positive or negative—of an oscillator output whose period is shorter than the preceding and following corresponding half-cycles. The glitch may also be characterized by an irregular shape and/or a voltage level different from the preceding and following corresponding half-cycles. Between time t4 and time t5, the oscillator 100 operates as described above for time t1 and time t2, but with the new capacitance value for the variable capacitors 105. At time t5, the oscillator 100 operates as described above for time t2. Between time t5 and time t6, the oscillator 100 operates as described above for time t0. After time t6, the cycle of time t4 to time t6 repeats.
The glitch between time t3 and time t4 may adversely affect the operation of components relying on the output signal 100o. Accordingly, it would be advantageous to have a glitch free relaxation oscillator